I have very mixed feelings about this book. On one hand, it provides some very valuable techniques for writing effective testbenches for HDL code. On the other hand, the book is written quite badly - in a very convoluted and disorganized style, with bizarre layout that wastes 40% of each page and diagrams any 5-year old could have drawn much better with just a little effort. The author tries to please everyone, by covering Verilog, VHDL, e and OpenVera! Yes, all of that. Of course, Verilog and VHDL are mutually exclusive in 99% of projects. So are OpenVera and e, so chances are that you're going to have to work quite hard just to find the information that interests you in this book. I, for example, was only interested in VHDL, which immediately rendered about 60% of the book useless for me. And as I've mentioned, the layout and diagrams are horrible. Come on, I have books from the 60s and the 70s with much prettier diagrams that actually help understanding, and aren't there just as fillers! It's hard to avoid criticism, as you see. But I began the review on a positive note, and I will end it similarly. Hidden deep inside all the chaff, there's some good advice there, and methods that must be familiar to verification engineers that hope to undertake complex verification tasks. In particular, Chapter 5 is probably the most important in the book. Chapter 6 is also quite good, so if you want to save time, read just those two.


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