Comments on: Parsing VHDL is [very] hard http://eli.thegreenplace.net/2009/05/19/parsing-vhdl-is-very-hard/ Eli Bendersky's personal website Wed, 28 Jul 2010 12:22:47 +0000 http://wordpress.org/?v=2.9.2 hourly 1 By: eliben http://eli.thegreenplace.net/2009/05/19/parsing-vhdl-is-very-hard/comment-page-1/#comment-211847 eliben Fri, 02 Oct 2009 06:15:45 +0000 http://eli.thegreenplace.net/?p=1696#comment-211847 pedro, I don't believe ANTLR is a silver bullet for VHDL parsing. First you have to plan how to address the cross-file context sensitivities I pointed to in the post, and perhaps others I haven't run into yet. pedro, I don’t believe ANTLR is a silver bullet for VHDL parsing. First you have to plan how to address the cross-file context sensitivities I pointed to in the post, and perhaps others I haven’t run into yet.

]]> By: pedro http://eli.thegreenplace.net/2009/05/19/parsing-vhdl-is-very-hard/comment-page-1/#comment-211492 pedro Wed, 30 Sep 2009 22:48:55 +0000 http://eli.thegreenplace.net/?p=1696#comment-211492 Eli, I'm looking for a tool to convert structural vhdl into a netlist file for printed circuit design. Currently standard practice is still to use graphical schematic editors for doing this but I want to bring this task into the 21st century and use text based entry. I am willing to do some work to achieve this but I was hoping antlr would get me part way there. Do you still believe antllr is not a worthwhile approach? Pedro Eli,

I’m looking for a tool to convert structural vhdl into a netlist file for printed circuit design. Currently standard practice is still to use graphical schematic editors for doing this but I want to bring this task into the 21st century and use text based entry.

I am willing to do some work to achieve this but I was hoping antlr would get me part way there. Do you still believe antllr is not a worthwhile approach?

Pedro

]]> By: eliben http://eli.thegreenplace.net/2009/05/19/parsing-vhdl-is-very-hard/comment-page-1/#comment-186956 eliben Mon, 27 Jul 2009 15:01:26 +0000 http://eli.thegreenplace.net/?p=1696#comment-186956 ANTLR won't help here - the problems are different. There's too much context sensitivity and inter-dependency between files. For pure parsing power PLY is sufficient here. ANTLR won’t help here – the problems are different. There’s too much context sensitivity and inter-dependency between files. For pure parsing power PLY is sufficient here.

]]> By: Claude BIDEAU http://eli.thegreenplace.net/2009/05/19/parsing-vhdl-is-very-hard/comment-page-1/#comment-186939 Claude BIDEAU Mon, 27 Jul 2009 14:17:22 +0000 http://eli.thegreenplace.net/?p=1696#comment-186939 Have you check the possibility to realize a VHDL Parser with tools as ANTLR http://antlr.org/ which is possible to interface with python? ps :As you, I'm very interested to parse VHDL for code analyze. I'm looking up into your PYCPARSER to known your "lex/yacc" schematic before to see your blog and your interest for the VHDL. BR Have you check the possibility to realize a VHDL Parser with tools as ANTLR
http://antlr.org/ which is possible to interface with python?

ps :As you, I’m very interested to parse VHDL for code analyze.
I’m looking up into your PYCPARSER to known your “lex/yacc” schematic before to see your blog and your interest for the VHDL.

BR

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