This is the Hardware::VHDL::Parser (CPAN) module. It uses Parse::RecDescent, for which the full VHDL grammar is a bit too much. Parse::RD is a terrific module, but it's slow on large grammars, unfortunately. This also rules out the possibility of me using it for my parser.
The alternative I see at the moment is Parse::YAPP. It uses Yacc's style parsing - LARL, instead of recursive descent, and is said to be much faster. Besides, it generates Perl code from its grammar, so the generation is only done once in a lifetime - each time the script runs it uses just the parser generated code.
I'm not final about this yet, looking at other options. If I indeed complete this task and manage to produce a quick VHDL parser, I'll consider loading it to CPAN as an alternative to the existing module which isn't too usable.Update (13.02.2009): these intentions led nowhere, and since then I've abandoned Perl as my main development language. But now I'm working on a VHDL parser in Python, so stay tuned to the blog to see if there's any progress.