a VHDL parser in Perl

October 24th, 2004 at 8:44 pm

For some time now I’ve been thinking of implementing a VHDL parser in Perl. I don’t want to reinvent the wheel here, but the only available parser I found is far too slow to be useful.

This is the Hardware::VHDL::Parser (CPAN) module. It uses Parse::RecDescent, for which the full VHDL grammar is a bit too much. Parse::RD is a terrific module, but it’s slow on large grammars, unfortunately. This also rules out the possibility of me using it for my parser.

The alternative I see at the moment is Parse::YAPP. It uses Yacc’s style parsing – LARL, instead of recursive descent, and is said to be much faster. Besides, it generates Perl code from its grammar, so the generation is only done once in a lifetime – each time the script runs it uses just the parser generated code.

I’m not final about this yet, looking at other options. If I indeed complete this task and manage to produce a quick VHDL parser, I’ll consider loading it to CPAN as an alternative to the existing module which isn’t too usable.

Update (13.02.2009): these intentions led nowhere, and since then I’ve abandoned Perl as my main development language. But now I’m working on a VHDL parser in Python, so stay tuned to the blog to see if there’s any progress.

Related posts:

  1. Parsing VHDL is [very] hard
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4 Responses to “a VHDL parser in Perl”

  1. Ernst BNo Gravatar Says:


    I am needing a Perl VHDL parser.
    What is the current status (June/2008) of your parser?
    Where can I obtain it and is there any documentation available?

    Thanks for your help,

    –Ernst B

  2. elibenNo Gravatar Says:

    Hi Ernst,
    I ended up dropping the endeavor, because it was very difficult and because I had no *real* use for it at the time.
    VHDL is one of the most difficult languages to process, because its grammar is huge.

  3. meowsqueakNo Gravatar Says:

    I’d be interested in your python VHDL parser – I’m looking for a (small?) utility to deduce a dependency tree for a set of VHDL files according to the VHDL Language Reference Manual section 13.5 – i.e. units need to be analysed before the unit that references them is.

    This tree would then be used by a Makefile to determine a compilation order.

    Do you have anything I could base such a script on please? Where would a good place to start be? I don’t think I need to handle the entire grammar – just need to locate references.

  4. elibenNo Gravatar Says:


    I’m working on it, so just stay tuned to this blog. I can’t say for sure when it will be done – may take a couple of months, maybe more.