… is really cool and makes life simpler !

So I have a block I have to verify. It sits on a bus with a processor and awaits input. I must verify that all its registers are correctly mapped to memory - write into a register, read from it and see it’s the same data.

First, I code (VHDL) a simple model of the bus interface to feed transactions to the bus. It reads vectors from a file and initiates transactions. But going over all vectors and verifying that the registers returned correct data is boring !!

Perl to the rescue ! For each write transaction, expect a read and just test that the output file is correct (some cool pack() and unpack() hacking to decode the bits).

But hmm… why not generate the reads automatically from writes ? Easy, with Perl of course.

I really feel how my programming experience allows me to be a more efficient hardware engineer. You don’t want to know about the horrors other engineers (no-no’s in programming) do for “automatic” verification.

PS: I’m now hacking an automatic test-bench generation from a given module entity. This requires superficial parsing of a VHDL file. As any parsing, at first it seems simple, but pretty quickly you stumble into problems unsolvable without a full-blown parser…

Related posts:

1. test vectors generation in Perl
2. programming geek - EE geek
3. Book review: “RTL Hardware design using VHDL” by Pong P. Chu
4. Perl scripting of Scite
5. hardware acceleration of algorithms

This entry was posted on Friday, May 16th, 2003 at 2:18 pm and is filed under EE / Embedded, Perl. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.